NXP Semiconductors /LPC18xx /ETHERNET /MAC_DEBUG

When high, it indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state.

When high, it indicates the active state of the small FIFO Read and Write controllers respectively of the MAC receive Frame Controller module.

Reserved

When high, it indicates that the MTL RxFIFO Write Controller is active and transferring a received frame to the FIFO.

State of the RxFIFO read Controller: 00 = idle state 01 = reading frame data 10 = reading frame status (or Time stamp) 11 = flushing the frame data and status

Reserved

Status of the RxFIFO Fill-level 00 = RxFIFO Empty 01 = RxFIFO fill-level below flow-control de-activate threshold 10 = RxFIFO fill-level above flow-control activate threshold 11 = RxFIFO Full

Reserved

When high, it indicates that the MAC MII transmit protocol engine is actively transmitting data and not in IDLE state.

State of the MAC Transmit Frame Controller module: 00 = idle 01 = Waiting for Status of previous frame or IFG/backoff period to be over 10 = Generating and transmitting a PAUSE control frame (in full duplex mode) 11 = Transferring input frame for transmission

When high, it indicates that the MAC transmitter is in PAUSE condition (in full-duplex only) and hence will not schedule any frame for transmission.

State of the TxFIFO read Controller 00 = idle state 01 = READ state (transferring data to MAC transmitter) 10 = Waiting for TxStatus from MAC transmitter 11 = Writing the received TxStatus or flushing the TxFIFO

When high, it indicates that the TxFIFO Write Controller is active and transferring data to the TxFIFO.

Reserved

When high, it indicates that the TxFIFO is not empty and has some data left for transmission.

When high, it indicates that the TxStatus FIFO is full and hence the controller will not be accepting any more frames for transmission.

Reserved